1. Field of the Invention
The present invention relates to a substrate for packing a semiconductor device, especially a high frequency semiconductor device, and a method for packing the semiconductor device in the packing substrate.
2. Related Arts
FIG. 1 illustrates a conventional semiconductor device packing substrate for packing a high frequency semiconductor device which works at a microwave or millimeter wave band. A first ceramic layer 101, a metal layer 102, a second ceramic layer 103, a wiring layer 104, and a third ceramic layer 105 are in turn laminated or provided to construct a multilayer ceramic substrate. A portion of the second ceramic layer 103, the wiring layer 104 and the third ceramic layer 105 is selectively removed off to form a cavity 106. A semiconductor device 107 on which an electrode pad 108 is provided is mounted on the metal layer 102 exposed by forming the cavity 106. In this case, the wiring layer 104 is used as an inner layer wiring, and is connected to the electrode pad 108 through a bonding wire 109. The length of the bonding wire 109 is several hundred .mu.m, and consequently inductance owing to the bonding wire increases to make transmission of signals difficult at an operation frequency within, especially, a millimeter wave band or higher frequency band. In order to ensure that the cavity has an area into which a semiconductor device is inserted, it is necessary to make the size of the cavity larger than that of the semiconductor device. Therefore, the position where the semiconductor device is packed inside the cavity 106 is varied and the length of the bonding wire 109 is also varied. As a result, various properties of the produced semiconductor devices are also varied, resulting in a drop in the yield rate thereof.
As an example of device in the prior art for that overcomes this problem, FIG. 2 illustrates a cross section of the main portion of a hybrid integrated circuit device disclosed in Japanese Patent Application Laid-Open No. 5-63136. In this case, a wiring layer 203 is disposed inside a cavity 202 formed in a multilayer substrate 201, and bump 204 is formed on the wiring layer 203. With the bump 204, the wiring layer 203 is electrically connected to an electrode pad 206 of a semiconductor device 205. Thus, the semiconductor device 205 is electrically connected to the wiring layer 203 with the small inductor element. This prior art example shows the structure of the hybrid integrated circuit device, but does not make any specific packing process clear.
The process for packing a semiconductor device by the aforementioned bump connection includes a process using the contractile force of a resin or the like for bonding, a thermo compression bonding process using compression accompanied with heating for bonding, and a hot melt process of thermally melting bumps for bonding. In all of these processes, however, an expensive position-aligning apparatus is necessary for precisely arranging semiconductor devices in the positions where the semiconductor devices are to be packed.
In the thermo compression bonding or hot melting process, position-aligning must be carried out with heating, and consequently, a large-scale apparatus becomes necessary. When plural elements are packed inside plural cavities in the same substrate, the elements must be packed one by one by using the position-aligning apparatus. For this reason, the packing-work takes a long time, and for semiconductor devices having low heat-resistance, various properties are deteriorated.
The process using the contractile force of a resin or the like has another problem in that a high frequency property is deteriorated because of the fact that dielectric loss and parasite capacitance are enlarged by the resin at an operation frequency within, especially, a millimeter wave band or higher frequency band.